Glass substrates are one of the tools Intel is counting on to continue Moore's Law.
While semiconductor lithography gets the bulk of the attention in chipmaking, other processes are equally important in producing working integrated circuits (ICs). Case in point: packaging. An IC package provides the electrical, thermal, and mechanical transition from the semiconductor die or chip to the circuit board, which is often called a motherboard. One key element of the IC package is the substrate, which is essentially a miniature circuit board with copper traces that bonds to the input/output (I/O), power and ground pads on the chip and electrically connects these pads to the circuit board. The substrate provides a solid mechanical home for the chip and is also thermally matched to the semiconductor chip’s thermal coefficient of expansion. Despite the importance of substrates, they’re usually treated as background players in the semiconductor theater. Integrated Chips
So, it was somewhat curious and unusual for Intel to make a major substrate announcement in preparation for this week’s Innovation event, being held in San Jose, California. The press release, dated September 18, says:
“Intel today announced one of the industry’s first glass substrates for next-generation advanced packaging, planned for the latter part of this decade. This breakthrough achievement will enable the continued scaling of transistors in a package and advance Moore’s Law to deliver data-centric applications.”
The release also quotes Babak Sabi, Intel senior vice president and general manager of Assembly and Test Development, who said: “After a decade of research, Intel has achieved industry-leading glass substrates for advanced packaging. We look forward to delivering these cutting-edge technologies that will benefit our key players and foundry customers for decades to come.”
Research into using glass substrates for chipmaking is nothing new. As Intel’s release says, the company has been working on this technology for at least a decade, as have other organizations such as the 3D Systems Packaging Research Center located at Georgia Tech, which was founded in 1994 – nearly 30 years ago. Last year, the Georgia Tech PRC launched an industry advisory board with Intel Fellow Ravi Mahajan as one of the initial board members. Intel has already spent more than a billion dollars to develop a glass-substrate manufacturing facility at its site in Chandler, Arizona.
A glass panel holds dozens of glass substrates at Intel's R&D facility in Chandler, Arizona.
So, if glass IC substrates are nothing new, why would Intel announce this particular development now, after ten years of corporate development and several years before these substrates find their way into products? On the technical side, it’s because existing ceramic and organic substrates are reaching the end of their ability to provide the electrical, thermal, and mechanical transitions for today’s most advanced semiconductors, which is doubly true as the industry adopts chiplets as an increasingly common way to put more transistors into a package.
Electrically, Intel expects to get a 10X boost in the number of connections it can make to a semiconductor die using glass substrates when compared to ceramic or organic substrates. That increase in the number of connections to a semiconductor die translate into more I/O connections to the underlying circuit board, more connections between and among chiplets, and more chiplets in a package because of the increased interconnect density. Glass substrates also readily accept electro-optical components such as fiber-optic transceivers, which promise much faster I/O speeds for IC-to-IC communications over longer distances than copper wiring. Intel has been working on integrated optics for years and that’s an I/O technology that is clearly on the company’s development horizon. (See “Intel Builds Eight-Channel Wavelength Division Multiplexed Laser Array On A Silicon Chip.”)
From the thermal and mechanical perspectives, glass substrates tolerate heat better than the substrate materials in common use today. Because glass is essentially silicon dioxide, it has a thermal coefficient of expansion similar to that of the silicon chips that are attached to the substrate, so there’s a better thermal match between the substrate and the semiconductor die, which means that the substrate and the semiconductor die will tend to stay coplanar and therefore reliably connected when the IC is operating and generating heat. This characteristic becomes increasingly important for the larger semiconductor die being manufactured today, and for future ICs that package even more chiplets on the same substrate.
The use of glass substrates in chipmaking is still years from production. As Intel’s press release states:
“By the end of the decade, the semiconductor industry will likely reach its limits on being able to scale transistors on a silicon package using organic materials, which use more power and include limitations like shrinkage and warping. Scaling is crucial to the progress and evolution of the semiconductor industry, and glass substrates are a viable and essential next step for the next generation of semiconductors.”
So why announce a technology today that’s still years away from production? It’s all part and parcel to the rebuilding of Intel’s battered brand as the world’s leading chipmaker. When Pat Gelsinger assumed the CEO mantle at Intel, he found that the corporate foundation of the house that Noyce, Moore, and Grove built needed repair. Intel was no longer considered the leader it had been. Other companies, including TSMC and Samsung, had taken over the lithographic lead. This packaging announcement is one brick in the Intel foundation.
Intel is conducting a multi-faceted rebuilding program that includes building new fabs around the world, speed-marching semiconductor technology development into an accelerated cycle, pushing its way to the head of the line for ASML’s new EXE:5000 high-NA EUV lithographic systems, introducing RibbonFETs (gate-all-around or GAA FETs) and PowerVia backside power delivery network (PDN) technologies to further increase chip performance, development of advanced IC packaging technologies including the use of chiplets and glass substrates, and adding integrated optics for high-speed I/O. All these technologies are essential tools for a once-and-future chipmaking leader.
Pcbway Assembly Service The author and members of the Tirias Research staff do not actively trade stock positions in any of the companies mentioned in this article. Tirias Research tracks and consults for companies throughout the electronics ecosystem from semiconductors to systems and sensors to the cloud. Tirias Research has consulted for Intel and several of the TIRIAS Research analysts have worked for semiconductor companies including Intel and AMD.